Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
896 Datasheet
23.5.4 PCISTS—PCI Device Status Register (IDER—D22:F2)
Address Offset: 06–07h Attribute: RO
Default Value: 00B0h Size: 16 bits
23.5.5 RID—Revision Identification Register (IDER—D22:F2)
Address Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
23.5.6 CC—Class Codes Register (IDER—D22:F2)
Address Offset: 09–0Bh Attribute: RO
Default Value: 010185h Size: 24 bits
23.5.7 CLS—Cache Line Size Register (IDER—D22:F2)
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
15:11 Reserved
10:9
DEVSEL# Timing Status (DEVT)—RO. This bit controls the device select time for
the PT function's PCI interface.
8:5 Reserved
4
Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer
implemented in the device.
3
Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the
function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when
this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host.
2:0 Reserved
Bit Description
7:0
Revision ID—RO. See the Intel
®
6 Series Chipset Specification Update for the value
of the RID Register.
Bit Description
23:16
Base Class Code (BCC)—RO This field indicates the base class code of the IDER
host controller device.
15:8
Sub Class Code (SCC)—RO This field indicates the sub class code of the IDER host
controller device.
7:0
Programming Interface (PI)—RO This field indicates the programming interface of
the IDER host controller device.
Bit Description
7:0 Cache Line Size (CLS)—RO. All writes to system memory are Memory Writes.
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