Datasheet 901
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.5.19 PMCS—PCI Power Management Control and Status
Register (IDER—D22:F2)
Address Offset: CC-CFh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
23.5.20 MID—Message Signaled Interrupt Capability ID
Register (IDER—D22:F2)
Address Offset: D0–D1h Attribute: RO
Default Value: 0005h Size: 16 bits
Bit Description
31:4 Reserved
3
No Soft Reset (NSR) — RO. When set to 1, this bit indicates that devices
transitioning from D3hot to D0 because of PowerState commands do not perform an
internal reset. Configuration Context is preserved. Upon transition from the D3hot to
the D0 Initialized state, no additional operating system intervention is required to
preserve Configuration Context beyond writing the PowerState bits.
When cleared to 0, devices do perform an internal reset upon transitioning from
D3hot to D0 using software control of the PowerState bits. Configuration Context is
lost when performing the soft reset. Upon transition from the D3hot to the D0 state,
full re-initialization sequence is needed to return the device to D0 Initialized.
Value in this bit is reflects chicken bit in ME-AUX register x13900, bit [7] which is as
follows:
0 = Device performs internal reset
1 = Device does not perform internal reset
2Reserved
1:0
Power State (PS)— R/W. This field is used both to determine the current power
state of the PT function and to set a new power state. The values are:
00 = D0 state
11 = D3
HOT
state
When in the D3
HOT
state, the controller's configuration space is available, but the I/O
and memory spaces are not. Additionally, interrupts are blocked. If software attempts
to write a '10' or '01' to these bits, the write will be ignored.
Bit Description
15:8
Next Pointer (NEXT) — RO. This value indicates this is the last item in the
capabilities list.
7:0
Capability ID (CID) — RO. The Capabilities ID value indicates device is capable of
generating an MSI.
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