Datasheet 905
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.6.4 IDEFR—IDE Features Register
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Feature register of the command block of the IDE
function. This register can be written only by the Host.
When the HOST reads the same address, it reads the Error register of Device 0 or
Device 1 depending on the device_select bit (bit 4 of the drive/head register).
23.6.5 IDESCIR—IDE Sector Count In Register
(IDER—D22:F2)
Address Offset: 02h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Sector Count register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDESCIR, IDESCOR0, IDESCOR1) are updated with the written
value.
A host read to this register address reads the IDE Sector Count Out Register IDESCOR0
if DEV=0 or IDESCOR1 if DEV=1
23.6.6 IDESCOR1—IDE Sector Count Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 02h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the HOST interface if DEV = 1. ME-Firmware writes to this
register at the end of a command of the selected device.
When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this
register is updated.
Bit Description
7:0 IDE Feature Data (IDEFD) — R/W. IDE drive specific data written by the Host
Bit Description
7:0
IDE Sector Count Data (IDESCD)— R/W. Host writes the number of sectors to be
read or written.
Bit Description
7:0
IDE Sector Count Out Dev1 (ISCOD1) — R/W. Sector Count register for Slave
Device (that is, Device 1)
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