Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 904

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
904 Datasheet
23.6.1 IDEDATA—IDE Data Register (IDER—D22:F2)
Address Offset: 0h Attribute: R/W
Default Value: 00h Size: 8 bits
The IDE data interface is a special interface that is implemented in the HW. This data
interface is mapped to IO space from the host and takes read and write cycles from the
host targeting master or slave device.
Writes from host to this register result in the data being written to ME memory.
Reads from host to this register result in the data being fetched from ME memory.
Data is typically written/ read in WORDs. ME-FW must enable hardware to allow it to
accept Host initiated Read/ Write cycles, else the cycles are dropped.
23.6.2 IDEERD1—IDE Error Register DEV1
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 1 (slave device).
23.6.3 IDEERD0—IDE Error Register DEV0
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 0 (master device).
Bit Description
7:0
IDE Data Register (IDEDR) — R/W. Data Register implements the data interface
for IDE. All writes and reads to this register translate into one or more corresponding
write/reads to ME memory
Bit Description
7:0
IDE Error Data (IDEED) — R/W. Drive reflects its error/ diagnostic code to the host
using this register at different times.
Bit Description
7:0
IDE Error Data (IDEED)— R/W. Drive reflects its error/ diagnostic code to the host
using this register at different times.