Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 909

Datasheet 909
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.6.13 IDCLOR0—IDE Cylinder Low Out Register Device 0
Register (IDER—D22:F2)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEV = 0. ME-Firmware writes to this register at the
end of a command of the selected device. When the host writes to the IDE Cylinder Low
In Register (IDECLIR), this register is updated with that value.
23.6.14 IDCHOR0—IDE Cylinder High Out Register Device 0
Register (IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEVice = 0. ME-Firmware writes to this register at
the end of a command of the selected device. When the host writes to the IDE Cylinder
High In Register (IDECHIR), this register is updated with that value.
Bit Description
7:0
IDE Cylinder Low Out DEV 0. (IDECLO0) — R/W. Cylinder Low Out Register for
Master Device.
Bit Description
7:0
IDE Cylinder High Out DEV 0 (IDECHO0) — R/W. Cylinder High out register for
Master device.