Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
910 Datasheet
23.6.15 IDCHOR1—IDE Cylinder High Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if Device = 1. ME-Firmware writes to this register at
the end of a command of the selected device. When the host writes to the IDE Cylinder
High In Register (IDECHIR), this register is updated with that value.
23.6.16 IDECHIR—IDE Cylinder High In Register
(IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Cylinder High register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDECHIR, IDECHOR0, IDECHOR1) are updated with the written
value.
Host read to this register address reads the IDE Cylinder High Out Register IDECHOR0
if DEV=0 or IDECHOR1 if DEV=1.
Bit Description
7:0
IDE Cylinder High Out DEV 1 (IDECHO1) — R/W. Cylinder High out register for
Slave device.
Bit Description
7:0
IDE Cylinder High Data (IDECHD) — R/W. Cylinder High data register for IDE
command block.
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