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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 923

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Datasheet 923
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.9.1 VVID—Vendor Identification Register (KT—D22:F3)
Address Offset: 00–01h Attribute: RO
Default Value: 8086h Size: 16 bits
23.9.2 DID—Device Identification Register (KT—D22:F3)
Address Offset: 02–03h Attribute: RO
Default Value: See bit description Size: 16 bits
23.9.3 CMD—Command Register Register (KT—D22:F3)
Address Offset: 04–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:0 Vendor ID (VID) RO. This is a 16-bit value assigned by Intel.
Bit Description
31:16
Device ID (DID) — RO. This is a 16-bit value assigned to the PCH KT controller. See
the Intel
®
6 Series Chipset Specification Update for the value of the DID Register.
Bit Description
15:11 Reserved
10
Interrupt Disable (ID)— R/W. This bit disables pin-based INTx# interrupts. This bit
has no effect on MSI operation.
1 = Internal INTx# messages will not be generated.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
enabled.
9:3 Reserved
2
Bus Master Enable (BME)— R/W. This bit controls the KT function's ability to act as
a master for data transfers. This bit does not impact the generation of completions
for split transaction commands. For KT, the only bus mastering activity is MSI
generation.
1
Memory Space Enable (MSE)— R/W. This bit controls Access to the PT function's
target memory space.
0
I/O Space enable (IOSE)— R/W. This bit controls access to the PT function's target
I/O space.

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