Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 924

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
924 Datasheet
23.9.4 STS—Device Status Register (KT—D22:F3)
Address Offset: 06–07h Attribute: RO
Default Value: 00B0h Size: 16 bits
23.9.5 RID—Revision ID Register (KT—D22:F3)
Address Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
23.9.6 CC—Class Codes Register (KT—D22:F3)
Address Offset: 09–0Bh Attribute: RO
Default Value: 070002h Size: 24 bits
Bit Description
15:11 Reserved
10:9
DEVSEL# Timing Status (DEVT)— RO. This field controls the device select time for
the PT function's PCI interface.
8:5 Reserved
4
Capabilities List (CL)— RO. This bit indicates that there is a capabilities pointer
implemented in the device.
3
Interrupt Status (IS)— RO. This bit reflects the state of the interrupt in the
function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when
this bit is a 1 and ID bit is 0 is the INTB interrupt asserted to the Host.
2:0 Reserved
Bit Description
7:0
Revision ID (RID)— RO. See the Intel
®
6 Series Chipset Specification Update for
the value of the RID Register.
Bit Description
23:16
Base Class Code (BCC)—RO This field indicates the base class code of the KT host
controller device.
15:8
Sub Class Code (SCC)—RO This field indicates the sub class code of the KT host
controller device.
7:0
Programming Interface (PI)—RO This field indicates the programming interface of
the KT host controller device.