Datasheet 925
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.9.7 CLS—Cache Line Size Register (KT—D22:F3)
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
This register defines the system cache line size in DWORD increments. Mandatory for
master which use the Memory-Write and Invalidate command.
23.9.8 KTIBA—KT IO Block Base Address Register
(KT—D22:F3)
Address Offset: 10–13h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
23.9.9 KTMBA—KT Memory Block Base Address Register
(KT—D22:F3)
Address Offset: 14–17h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
7:0 Cache Line Size (CLS)— RO. All writes to system memory are Memory Writes.
Bit Description
31:16 Reserved
15:3
Base Address (BAR)— R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE)— RO. This bit indicates a request for I/O space
Bit Description
31:12
Base Address (BAR)— R/W. This field provides the base address for Memory
Mapped I,O BAR. Bits 31:12 correspond to address signals 31:12.
11:4 Reserved
3 Prefetchable (PF)— RO. This bit indicates that this range is not pre-fetchable.
2:1
Type (TP)— RO. This field indicates that this range can be mapped anywhere in 32-
bit address space.
0
Resource Type Indicator (RTE)— RO. This bit indicates a request for register
memory space.
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