Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 99
PCH Pin States
GPIO31
9
(Non Deep-S4/
S5 mode)
DSW High-Z (Input) High-Z (Input) Defined Defined Defined
GPIO31
9
(Deep-S4/S5
mode)
DSW High-Z (Input) High-Z (Input) Defined Defined Defined
GPIO33
9
Core High High High Off Off
GPIO35 Core Low Low Defined Off Off
SPI Interface
SPI_CS0# ASW High
12
High Defined Defined Defined
SPI_CS1#
7
ASW High
12
High Defined Defined Defined
SPI_MOSI
7
ASW Low
12
Low Defined Defined Defined
SPI_CLK ASW Low
12
Low Running Defined Defined
Controller Link
CL_CLK1
6
Suspend High/Low
15
High/Low
15
Defined Defined Defined
CL_DATA1
6
Suspend High/Low
15
High/Low
15
Defined Defined Defined
CL_RST1#
6
Suspend Low High High High High
Thermal Signals
PECI Processor Low Low Defined Off Off
Analog Display / CRT DAC Signals
VGA_RED, VGA_GREEN,
VGA_BLUE
Core High-Z High-Z High-Z Off Off
DAC_IREF Core High-Z Low Low Off Off
VGA_HSYNC Core Low Low Low Off Off
VGA_VSYNC Core Low Low Low Off Off
VGA_DDC_CLK Core High-Z High-Z High-Z Off Off
VGA_DDC_DATA Core High-Z High-Z High-Z Off Off
VGA_IRTN Core High-Z High-Z High-Z Off Off
Intel
®
Flexible Display Interface
FDI_FSYNC[1:0] Core High-Z High-Z High-Z Off Off
FDI_LSYNC[1:0] Core High-Z High-Z High-Z Off Off
FDI_INT Core High-Z High-Z High-Z Off Off
Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 5 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
S0/S1 S3 S4/S5