Rev. 1.50, 10/04, page 110 of 448
6.5.3 FPU Exception Handling
FPU exception handling is initiated in the following cases:
• FPU error (E): FPSCR.DN = 0 and a denormalized number is input
• Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation)
• Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor or the input of
FSRRA is zero
• Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result
overflow
• Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result
underflow
• Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation
result
All exception events that originate in the FPU are assigned as the same exception event. The
meaning of an exception is determined by software by reading from FPSCR and interpreting the
information it contains. Also, the destination register is not changed by any FPU exception
handling operation.
If the FPU exception sources except for above are generated, the bit corresponding to source V, Z,
O, U, or I is set to 1, and a default value is generated as the operation result.
• Invalid operation (V): qNaN is generated as the result.
• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
• Overflow (O):
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
• Underflow (U):
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value, or
zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
• Inexact exception (I): An inexact result is generated.
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