Rev. 1.50, 10/04, page 146 of 448
6. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
7.6 Memory-Mapped TLB Configuration
To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read
from and written to by a program in the P2 area with a MOV instruction in privileged mode.
Operation is not guaranteed if access is made from a program in another area.
After the memory-mapped TLB has been accessed, execute one of the following three methods
before an access (including an instruction fetch) to an area other than the P2 area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be an area
other than the P2 area.
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the MT bit in IRMCR is 0 (initial value) before accessing the memory-mapped TLB, the
specific instruction does not need to be executed. However, note that the CPU processing
performance will be lowered because the instruction fetch is performed again for the next
instruction after MMUCR has been updated.
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
The ITLB and UTLB are allocated to the P4 area in the virtual address space. VPN, V, and ASID
in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as a data array. VPN,
D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and
SH as a data array. V and D can be accessed from both the address array side and the data array
side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For
reserved bits, a write value of 0 should be specified; their read value is undefined.
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