Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 195 of 448
9.2.5 L Memory Transfer Destination Address Register 1 (LDA1)
When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical
address for block transfer to page 1 in the L memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit :
000
Initial value :
R R R R/W R/W R/W R/W R/W R/W R/W
L1DADR
L1DADR L1DSZ
R/W R/W R/W R/W R/W R/W
R/W:
151413121110987654321
0
Bit :
00
0
0
Initial value :
R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 29 — All 0 R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
28 to 10 L1DADR Undefined R/W L Memory Page 1 Block Transfer Destination Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify transfer destination physical address for block
transfer to page 1 in the L memory.
9 to 6 — All 0 R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.