Renesas SuperH SH-4A - TAS (Test and Set): Logical Instruction

Rev. 1.50, 10/04, page 334 of 448
10.1.77 TAS (Test And Set): Logical Instruction
Format Operation Instruction Code Cycle T Bit
TAS.B @Rn If (Rn) = 0, 1 → T, else 0 → T
1 → MSB of (Rn)
0100nnnn00011011 4 Test result
Description: This instruction purges the cache block corresponding to the memory area specified
by the contents of general register Rn, reads the byte data indicated by that address, and sets the T
bit to 1 if that data is zero, or clears the T bit to 0 if the data is nonzero. The instruction then sets
bit 7 to 1 and writes to the same address. The bus is not released during this period.
The purge operation is executed as follows.
In a purge operation, data is accessed using the contents of general register Rn as the effective
address. If there is a cache hit and the corresponding cache block is dirty (U bit = 1), the contents
of that cache block are written back to external memory, and the cache block is then invalidated
(by clearing the V bit to 0). If there is a cache hit and the corresponding cache block is clean (U bit
= 0), the cache block is simply invalidated (by clearing the V bit to 0). A purge is not executed in
the event of a cache miss, or if the accessed memory location is non-cacheable.
The two TAS.B memory accesses are executed automatically. Another memory access is not
executed between the two TAS.B accesses.
Notes: None
Operation:
TAS(int n) /* TAS.B @Rn */
{
int temp;
temp = (int)Read_Byte(R[n]); /* Bus Lock */
if (temp==0) T = 1;
else T = 0;
temp |= 0x00000080;
Write_Byte(R[n],temp); /* Bus unlock */
PC += 2;
}