Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 223 of 448
10.1.13 CLRT (Clear T Bit): System Control Instruction
Format Operation Instruction Code Cycle T Bit
CLRT 0 → T 0000000000001000 1 0
Description: This instruction clears the T bit.
Notes: None
Operation:
CLRT( ) /* CLRT */
{
T = 0;
PC += 2;
}
Example:
CLRT ;Before execution T = 1
;After execution T = 0

Renesas SuperH SH-4A Specifications

General

Architecture	32-bit RISC
Core	SH-4A
Data Bus Width	32-bit
Instruction Set	SuperH
Cache	32 KB instruction, 32 KB data
Number of Registers	16 general-purpose, 16 control
MMU	Yes
Typical Applications	Embedded systems, automotive, consumer electronics
Manufacturing Process	90 nm
Voltage	1.2V core, 3.3V I/O
FPU	Yes
Package	BGA