Renesas SuperH SH-4A - AND (and Logical): Logical Instruction

Rev. 1.50, 10/04, page 208 of 448
10.1.4 AND (AND Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 1 —
AND #imm,R0 R0 & imm → R0 11001001iiiiiiii 1 —
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm →
(R0 + GBR)
11001101iiiiiiii 3 —
Description: This instruction ANDs the contents of general registers Rn and Rm and stores the
result in Rn.
This instruction can be used to AND general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to AND 8-bit memory with 8-bit
immediate data.
Notes: With AND #imm,R0, the upper 24 bits of R0 are always cleared as a result of the
operation.
Operation:
AND(long m, long n) /* AND Rm,Rn */
{
R[n] &= R[m];
PC += 2;
}
ANDI(long i) /* AND #imm,R0 */
{
R[0] &= (0x000000FF & (long)i);
PC += 2;
}
ANDM(long i) /* AND.B #imm,@(R0,GBR) */
{
long temp;
temp = (long)Read_Byte(GBR+R[0]);