Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 249 of 448
10.1.26 LDS (Load to System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDS Rm,MACH Rm → MACH 0100mmmm00001010 1 —
LDS Rm,MACL Rm → MACL 0100mmmm00011010 1 —
LDS Rm,PR Rm→ PR 0100mmmm00101010 1 —
LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 1 —
LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 1 —
LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1 —
Description: Stores the source operand into the system registers MACH, MACL, or PR.
Notes: None
Operation:
LDSMACH(long m) /* LDS Rm,MACH */
{
MACH = R[m];
PC += 2;
}
LDSMACL(long m) /* LDS Rm,MACL */
{
MACL = R[m];
PC += 2;
}
LDSPR(long m) /* LDS Rm,PR */
{
PR = R[m];
PC += 2;
}