Renesas SuperH SH-4A - FSCHG (Sz-Bit Change): Floating-Point Instruction

Rev. 1.50, 10/04, page 410 of 448
10.3.20 FSCHG (Sz-bit Change): Floating-Point Instruction
PR Format Operation Instruction Code Cycle T Bit
0 FSCHG ~FPSCR.SZ → FPSCR.SZ 1111001111111101 1 —
Description: This instruction inverts the SZ bit of the floating-point status register FPSCR.
Changing the value of the SZ bit in FPSCR switches the amount of data for transfer by the FMOV
instruction between one single-precision data and a pair of single-precision data. When FPSCR.SZ
= 0, an FMOV instruction transfers a single-precision number. When FPSCR.SZ = 1, the FMOV
instruction transfers a pair of single-precision numbers.
Notes: None
Operation:
void FSCHG() /* FSCHG */
{
if(FPSCR_PR == 0){
FPSCR ^= 0x00100000; /* bit 20 */
PC += 2;
}
else undefined_operation();
}
Possible Exceptions: None