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Renesas SuperH SH-4A

Renesas SuperH SH-4A
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Rev. 1.50, 10/04, page 283 of 448
10.1.40 MUL.L (Multiply Long): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
MUL.L Rm,Rn Rn × Rm MACL 0000nnnnmmmm0111 2 —
Description: This instruction performs 32-bit multiplication of the contents of general registers
Rn and Rm, and stores the lower 32 bits of the result in the MACL register. The contents of
MACH are not changed.
Notes: None
Operation:
MULL(long m, long n) /* MUL.L Rm,Rn */
{
MACL = R[n]*R[m];
PC += 2;
}
Example:
MUL.L R0,R1 ;Before execution R0 = H'FFFFFFFE, R1 = H'00005555
;After execution MACL = H'FFFF5556
STS MACL,R0 ;Get operation result

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