Rev. 1.50, 10/04, page 296 of 448
10.1.51 PREF (Prefetch Data to Cache): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
PREF @Rn (Rn) → operand cache 0000nnnn10000011 1 —
Description: This instruction reads a 32-byte data block starting at a 32-byte boundary into the
operand cache. The lower 5 bits of the address specified by Rn are masked to zero.
This instruction does not generate data address error and MMU exceptions except data TLB
multiple-hit exception. In the event of an error, the PREF instruction is treated as an NOP (no
operation) instruction.
Notes: None
Operation:
PREF(int n) /* PREF @Rn */
{
PC += 2;
}
Example:
MOV.L #SOFT_PF,R1 ;R1 address is SOFT_PF
PREF @R1 ;Load SOFT_PF data into on-chip cache
.align 32
SOFT_PF: .data.l H'12345678
.data.l H'9ABCDEF0
.data.l H'AAAA5555
.data.l H'5555AAAA
.data.l H'11111111
.data.l H'22222222
.data.l H'33333333
.data.l H'44444444
Possible Exceptions:
• Data TLB multiple-hit exception
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