Rev. 1.50, 10/04, page 251 of 448
10.1.27 LDTLB (Load PTEH/PTEL to TLB): System Control Instruction (Privileged
Instruction)
Format Operation Instruction Code Cycle T Bit
LDTLB PTEH/PTEL → TLB 0000000000111000 1 —
Description: This instruction loads the contents of the PTEH/PTEL registers into the TLB
(translation lookaside buffer) specified by MMUCR.URC (random counter field in the MMC
control register).
LDTLB is a privileged instruction, and can only be used in privileged mode. Use of this
instruction in user mode will cause an illegal instruction exception.
Notes: As this instruction loads the contents of the PTEH/PTEL registers into a TLB, it should be
used either with the MMU disabled, or in the P1 or P2 virtual space with the MMU enabled (see
section 7, Memory Management Unit (MMU), for details). After this instruction is issued, there
must be at least one instruction between the LDTLB instruction and issuance of an instruction
relating to address to the P0, U0, and P3 areas (i.e. BRAF, BSRF, JMP, JSR, RTS, or RTE).
Operation:
LDTLB( ) /*LDTLB */
{
TLB[MMUCR.URC].ASID = PTEH & 0x000000FF;
TLB[MMUCR.URC].VPN = (PTEH & 0xFFFFFC00) >> 10;
TLB[MMUCR.URC].PPN = (PTEH & 0x1FFFFC00) >> 10;
TLB[MMUCR.URC].SZ = (PTEL & 0x00000080) >> 6 |
(PTEL & 0x00000010) >> 4;
TLB[MMUCR.URC].SH = (PTEH & 0x00000002) >> 1;
TLB[MMUCR.URC].PR = (PTEH & 0x00000060) >> 5;
TLB[MMUCR.URC].WT = (PTEH & 0x00000001);
TLB[MMUCR.URC].C = (PTEH & 0x00000008) >> 3;
TLB[MMUCR.URC].D = (PTEH & 0x00000004) >> 2;
TLB[MMUCR.URC].V = (PTEH & 0x00000100) >> 8;
PC += 2;
}
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