Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 55 of 448
Instruction
Group Instruction
CO AND.B #imm,@(R0,GBR)
ICBI
LDC Rm,DBR
LDC Rm, SGR
LDC Rm,SR
LDC.L @Rm+,DBR
LDC.L @Rm+,SGR
LDC.L @Rm+,SR
LDTLB
MAC.L
MAC.W
MOVCO
MOVLI
OR.B #imm,@(R0,GBR)
PREFI
RTE
SLEEP
STC SR,Rn
STC.L SR,@-Rn
SYNCO
TAS.B
TRAPA
TST.B #imm,@(R0,GBR)
XOR.B #imm,@(R0,GBR)
[Legend]
R: Rm/Rn
@adr: Address
SR1: MACH/MACL/PR
SR2: FPUL/FPSCR
CR1: GBR/Rp_BANK/SPC/SSR/VBR
CR2: CR1/DBR/SGR
FR: FRm/FRn/DRm/DRn/XDm/XDn
The parallel execution of two instructions can be carried out under following conditions.
1. Both addr (preceding instruction) and addr+2 (following instruction) are specified within the
minimum page size (1 Kbyte).
2. The execution of these two instructions is supported in table 4.3, Combination of Preceding
and Following Instructions.
3. Data used by an instruction of addr does not conflict with data used by a previous instruction
4. Data used by an instruction of addr+2 does not conflict with data used by a previous
instruction
5. Both instructions are valid
Table 4.3 Combination of Preceding and Following Instructions
Preceding Instruction (addr)
EX MT BR LS FE CO
EX No Yes Yes Yes Yes
MT Yes Yes Yes Yes Yes
Following
Instruction
(addr+2)
BR Yes Yes No Yes Yes
LS Yes Yes Yes No Yes
FE Yes Yes Yes Yes No
CO No

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English