Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 56 of 448
4.3 Issue Rates and Execution Cycles
Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4
corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not
considered in the issue rates and execution cycles in this section.
1. Issue Rate
I1 I2 ID S1 S2 S3 WB
Issue rate: 3
E2S2 E3S3 WB
Issue rates indicates the issue period between one instruction and next instruction.
E.g. AND.B instruction
E1S1
I1 I2 ID S1 S2 S3
WB
MS
S2 S3 WB
S1
ID
ID
ID
(I1) (ID)(I2)
Next instruction
M3
M2
Issue rate: 2
(I1)
(ID)
(I2)
E.g. MAC.W instruction
Execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules.
CPU instruction
E.g. AND.B instruction
I1 I2 ID S1 S2 S3 WB
Execution Cycles: 3
E2S2 E3S3
WB
E1S1
ID
ID
I1 I2 ID S1 S2 S3
WB
MS
S2 S3 WB
S1
ID
M3
M2
E.g. MAC.W instruction
Execution Cycles: 4
2. Execution Cycles
Next instruction
FPU instruction
E.g. FMUL instruction
Execution Cycles: 14
E.g. FDIV instruction
FE1
FE2 FE3 FE4 FE5 FE6
FE1 FE2
FE3
FE4
FE5
FE6
FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
I1 I2
ID
I1
I2
ID
Divider occupation cycle
FS
FE3
FE4
FE5
FE6
FS
Execution Cycles: 3

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English