Rev. 1.50, 10/04, page 321 of 448
10.1.70 STC (Store Control Register): System Control Instruction (Privileged Instruction)
Format Operation Instruction Code Cycle T Bit
STC GBR, Rn GBR → Rn 0000nnnn00010010 1 —
STC VBR, Rn VBR → Rn 0000nnnn00100010 1 —
STC SSR, Rn SSR → Rn 0000nnnn00110010 1 —
STC SPC, Rn SPC → Rn 0000nnnn01000010 1 —
STC SGR, Rn SGR → Rn 0000nnnn00111010 1 —
STC DBR, Rn DBR → Rn 0000nnnn11111010 1 —
STC R0_BANK, Rn R0_BANK → Rn 0000nnnn10000010 1 —
STC R1_BANK, Rn R1_BANK → Rn 0000nnnn10010010 1 —
STC R2_BANK, Rn R2_BANK → Rn 0000nnnn10100010 1 —
STC R3_BANK, Rn R3_BANK → Rn 0000nnnn10110010 1 —
STC R4_BANK, Rn R4_BANK → Rn 0000nnnn11000010 1 —
STC R5_BANK, Rn R5_BANK → Rn 0000nnnn11010010 1 —
STC R6_BANK, Rn R6_BANK → Rn 0000nnnn11100010 1 —
STC R7_BANK, Rn R7_BANK → Rn 0000nnnn11110010 1 —
STC.L GBR, @-Rn Rn-4 → Rn, GBR → (Rn) 0100nnnn00010011 1 —
STC.L VBR, @-Rn Rn-4 → Rn, VBR → (Rn) 0100nnnn00100011 1 —
STC.L SSR, @-Rn Rn-4 → Rn, SSR → (Rn) 0100nnnn00110011 1 —
STC.L SPC, @-Rn Rn-4 → Rn, SPC → (Rn) 0100nnnn01000011 1 —
STC.L SGR, @-Rn Rn-4 → Rn, SGR → (Rn) 0100nnnn00110010 1 —
STC.L DBR, @-Rn Rn-4 → Rn, DBR → (Rn) 0100nnnn11110010 1 —
STC.L R0_BANK, @-Rn Rn-4 → Rn, R0_BANK → (Rn) 0100nnnn10000011 1 —
STC.L R1_BANK, @-Rn Rn-4 → Rn, R1_BANK → (Rn) 0100nnnn10010011 1 —
STC.L R2_BANK, @-Rn Rn-4 → Rn, R2_BANK → (Rn) 0100nnnn10100011 1 —
STC.L R3_BANK, @-Rn Rn-4 → Rn, R3_BANK → (Rn) 0100nnnn10110011 1 —
STC.L R4_BANK, @-Rn Rn-4 → Rn, R4_BANK → (Rn) 0100nnnn11000011 1 —
STC.L R5_BANK, @-Rn Rn-4 → Rn, R5_BANK → (Rn) 0100nnnn11010011 1 —
STC.L R6_BANK, @-Rn Rn-4 → Rn, R6_BANK → (Rn) 0100nnnn11100011 1 —
STC.L R7_BANK, @-Rn Rn-4 → Rn, R7_BANK → (Rn) 0100nnnn11110011 1 —
Description: This instruction stores control register GBR, VBR, SSR, SPC, SGR, DBR or
Rm_BANK (m = 0–7) in the destination.
Rm_BANK operands are specified by the RB bit of the SR register:
when the RB bit is 1 Rm_BANK0 is accessed,
when the RB bit is 0 Rm_BANK1 is accessed.
To Next Page
Loading...
