Rev. 1.50, 10/04, page 10 of 448
31 0
R0
_
BANK0*
1,
*
2
R1
_
BANK0*
2
R2
_
BANK0*
2
R3
_
BANK0*
2
R4
_
BANK0*
2
R5
_
BANK0*
2
R6
_
BANK0*
2
R7
_
BANK0*
2
R8
R9
R10
R11
R12
R13
R14
R15
SR
GBR
MACH
MACL
PR
PC
(a) Register configuration
in user mode
31 0
R0
_
BANK1*
1,
*
3
R1
_
BANK1*
3
R2
_
BANK1*
3
R3
_
BANK1*
3
R4
_
BANK1*
3
R5
_
BANK1*
3
R6
_
BANK1*
3
R7
_
BANK1*
3
R8
R9
R10
R11
R12
R13
R14
R15
R0
_
BANK0*
1,
*
4
R1
_
BANK0*
4
R2
_
BANK0*
4
R3
_
BANK0*
4
R4
_
BANK0*
4
R5
_
BANK0*
4
R6
_
BANK0*
4
R7
_
BANK0*
4
(b) Register configuration in
privileged mode (RB = 1)
GBR
MACH
MACL
VBR
PR
SR
SSR
PC
SPC
31 0
R0
_
BANK1*
1,
*
3
R1
_
BANK1*
3
R2
_
BANK1*
3
R3
_
BANK1*
3
R4
_
BANK1*
3
R5
_
BANK1*
3
R6
_
BANK1*
3
R7
_
BANK1*
3
R8
R9
R10
R11
R12
R13
R14
R15
R0
_
BANK0*
1,
*
4
R1
_
BANK0*
4
R2
_
BANK0*
4
R3
_
BANK0*
4
R4
_
BANK0*
4
R5
_
BANK0*
4
R6
_
BANK0*
4
R7
_
BANK0*
4
(c) Register configuration in
privileged mode (RB = 0)
GBR
MACH
MACL
VBR
PR
SR
SSR
PC
SPC
SGR
DBR
SGR
DBR
R0 is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
Banked registers
Banked registers
Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
Banked registers
Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only
by LDC/STC instructions when the RB bit is set to 1.
Notes: 1.
2.
3.
4.
Figure 2.2 CPU Register Configuration in Each Processing Mode
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