Rev. 1.50, 10/04, page 308 of 448
10.1.61 SHAD (Shift Arithmetic Dynamically): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHAD Rm, Rn When Rm ≥ 0,
Rn << Rm → Rn
When Rm < 0,
Rn >> Rm → [MSB → Rn]
0100nnnnmmmm1100 1 —
Description: This instruction arithmetically shifts the contents of general register Rn. General
register Rm specifies the shift direction and the number of bits to be shifted.
Rn register contents are shifted to the left if the Rm register value is positive, and to the right if
negative. In a shift to the right, the MSB is added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If
the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left
shift range is 0 to 31, and the right shift range, 1 to 32.
MSB LSB
0
MSB
Rm ≥ 0
Rm < 0
MSB
LSB
Notes: None
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