Renesas SuperH SH-4A - OR (or Logical): Logical Instruction

Rev. 1.50, 10/04, page 293 of 448
10.1.50 OR (OR Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 1 —
OR #imm,R0 R0 | imm → R0 11001011iiiiiiii 1 —
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm
→ (R0 + GBR)
11001111iiiiiiii 3 —
Description: This instruction ORs the contents of general registers Rn and Rm and stores the
result in Rn.
This instruction can be used to OR general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to OR 8-bit memory with 8-bit
immediate data.
Notes: None