Rev. 1.50, 10/04, page 121 of 448
7.2 Register Descriptions
The following registers are related to MMU processing.
Table 7.1 Register Configuration
Register Name Abbreviation R/W P4 Address*
Area 7
Address* Size
Page table entry high register PTEH R/W H'FF00 0000 H'1F00 0000 32
Page table entry low register PTEL R/W H'FF00 0004 H'1F00 0004 32
Translation table base register TTB R/W H'FF00 0008 H'1F00 0008 32
TLB exception address register TEA R/W H'FF00 000C H'1F00 000C 32
MMU control register MMUCR R/W H'FF00 0010 H'1F00 0010 32
Physical address space control
register
PASCR R/W H'FF00 0070 H'1F00 0070 32
Instruction re-fetch inhibit control
register
IRMCR R/W H'FF00 0078 H'1F00 0078 32
Note: * These P4 addresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Table 7.2 Register States in Each Processing State
Register Name Abbreviation
Power-on
Reset
Manual
Reset Sleep Standby
Page table entry high register PTEH Undefined Undefined Retained Retained
Page table entry low register PTEL Undefined Undefined Retained Retained
Translation table base register TTB Undefined Undefined Retained Retained
TLB exception address register TEA Undefined Retained Retained Retained
MMU control register MMUCR H'0000 0000 H'0000 0000 Retained Retained
Physical address space control
register
PASCR H'0000 0000 H'0000 0000 Retained Retained
Instruction re-fetch inhibit control
register
IRMCR H'0000 0000 H'0000 0000 Retained Retained
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