Rev. 1.50, 10/04, page 440 of 448
Item Page Revision (See Manual for Details)
7.2.2 Page Table Entry Low
Register (PTEL)
123 Added.
Bit Bit Name Initial Value R/W
0 WT  R/W
7.2.6 Physical Address Space
Control Register (PASCR)
128 Amended.
Bit
Bit
Name
Description
7 to 0 UB Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache
or in the cache write-through mode, these bits
specify whether the next bus access from the CPU
waits for the end of writing for each area.
0 : The CPU does not wait for the end of writing
bus access and starts the next bus access
1 : The CPU waits for the end of writing bus
access and starts the next bus access
7.2.7 Instruction Re-Fetch Inhibit
Control Register (IRMCR)
129,
130
Amended.
Bit Bit Name Initial Value R/W
4 R2 0
R/W
3 R1 0 R/W
2 LT 0 R/W
7.7 32-Bit Address Extended
Mode
151 to
158
Added.
Section 8 Caches 159 Note added.
8.5.1 Coherency between Cache
and External Memory
175 Deleted.
• 1Kbyte page size cannot be used.
• In the case of 64KB size operand cache, the bit [13]
of virtual address must be same as the bit [13] of
the physical address in 4KB page mode.
• In the case of 128KB size operand cache, the bits
[14:13] of virtual address must be same as the bits
[14:13] of the physical address in 4KB page mode.
8.6.1 IC Address Array 177 Note added.
8.6.3 OC Address Array 180 Note added.
To Next Page
Loading...
Need help?
General
