Renesas SuperH SH-4A - Figure 8.1 Configuration of Operand Cache (OC)

Rev. 1.50, 10/04, page 160 of 448
The operand cache of the SH-4A is 4-way set associative, each may comprising 256 cache lines.
Figure 8.1 shows the configuration of the operand cache.
The instruction cache is 4-way set-associative, each way comprising 256 cache lines. Figure 8.2
shows the configuration of the instruction cache.
31 54 2
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
6 bits
MMU
[12:5]
255 19 bits 1 bit 1 bit
Tag U V
Address array
(way 0 to way 3)
Data array
(way 0 to way3)
LRU
Entry selection
Longword (LW) selection
Virtual address
3
8
22
19
0
Write data
Read data
Hit signal
(Way 0 to way 3)
12 10
0
Comparison
Figure 8.1 Configuration of Operand Cache (OC)