Rev. 1.50, 10/04, page 190 of 448
9.2.2 L Memory Transfer Source Address Register 0 (LSA0)
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical
address for block transfer to page 0 of the L memory.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit :
000
Initial value :
R R R R/W R/W R/W R/W R/W R/W R/W
L0SADR
L0SADR L0SSZ
R/W R/W R/W R/W R/W R/W
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
Bit :
00
0
0
Initial value :
R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 29 — All 0 R Reserved
For read/write in these bits, refer General Precautions
on Handling of Product.
28 to 10 L0SADR Undefined R/W L Memory Page 0 Block Transfer Source Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify the transfer source physical address for block
transfer to page 0 in the L memory.
9 to 6 — All 0 R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
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