Rev. 1.50, 10/04, page 336 of 448
10.1.78 TRAPA (Trap Always): System Control Instruction
Format Operation Instruction Code Cycle T Bit
TRAPA #imm Imm<<2 → TRA, PC + 2 →
SPC, SR → SSR, R15 → SGR,
1 → SR.MD/BL/RB,
H'160 → EXPEVT,
VBR + H'00000100 → PC
11000011iiiiiiii 13 —
Description: This instruction starts trap exception handling. The values of (PC + 2), SR, and R15
are saved to SPC, SSR and SGR, and 8-bit immediate data is stored in the TRA register (bits 9 to
2). The processor mode is switched to privileged mode (the MD bit in SR is set to 1), and the BL
bit and RB bit in SR are set to 1. As a result, exception and interrupt requests are masked (not
accepted), and the BANK1 registers (R0_BANK1 to R7_BANK1) are selected. Exception code
H'160 is written to the EXPEVT register (bits 11 to 0). The program branches to address (VBR +
H'00000100), indicated by the sum of the VBR register contents and offset H'00000100.
Notes: None
Operation:
TRAPA(int i) /* TRAPA #imm */
{
int imm;
imm = (0x000000FF & i);
TRA = imm<<2;
SSR = SR;
SPC = PC+2;
SGR = R15;
SR.MD = 1;
SR.BL = 1;
SR.RB=1;
EXPEVT = 0x00000160;
PC = VBR + 0x00000100;
}
Possible Exceptions:
• Unconditional trap
• Slot illegal instruction exception
To Next Page
Loading...
