Renesas SuperH SH-4A - LDC (Load to Control Register): System Control Instruction (Privileged; (Privileged Instruction)

Rev. 1.50, 10/04, page 348 of 448
10.2.4 LDC (Load to Control Register): System Control Instruction (Privileged
Instruction)
Format Operation Instruction Code Cycle T Bit
LDC Rm,SR Rm → SR 0100mmmm00001110 4 LSB
LDC.L @Rm+,SR (Rm) → SR, Rm+4 → Rm 0100mmmm00000111 4 LSB
Description: This instruction stores the source operand in the control register SR.
Notes: This instruction is only usable in privileged mode. Issuing this instruction in user mode
will cause an illegal instruction exception.
Operation:
LDCSR(int m) /* LDC Rm,SR : Privileged */
{
SR = R[m] & 0x700083F3;
PC += 2;
}
LDCMSR(int m) /* LDC.L @Rm+,SR: Privileged */
{
SR = Read_Long(R[m]) & 0x700083F3;
R[m] += 4;
PC += 2;
}
Possible exception:
• Data TLB multiple-hit exception
• General illegal instruction exception
• Slot illegal instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error