Rev. 1.50, 10/04, page 133 of 448
• D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed
1: Write has been performed
• WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
31
• 1-Kbyte page
10 9 0
Virtual address
31
• 4-Kbyte page
12 11 0
Virtual address
31
• 64-Kbyte page
16 15 0
Virtual address
31
• 1-Mbyte page
20 19 0
Virtual address
VPN
Offset
VPN Offset
VPN Offset
VPN Offset
28 10 9 0
Physical address
28 12 11 0
Physical address
28 16 15 0
Physical address
28 20 19 0
Physical address
PPN Offset
PPN Offset
PPN Offset
PPN
Offset
Figure 7.7 Relationship between Page Size and Address Format
7.3.2 Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access.
Information in the address translation table located in the UTLB is cached into the ITLB. Figure
7.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries.
PPN[28:10]
PPN[28:10]
PPN[28:10]
PPN[28:10]
SZ[1:0]
SZ[1:0]
SZ[1:0]
SZ[1:0]
SH
SH
SH
SH
C
C
C
C
PR
PR
PR
PR
ASID[7:0]
ASID[7:0]
ASID[7:0]
ASID[7:0]
VPN[31:10]
VPN[31:10]
VPN[31:10]
VPN[31:10]
V
V
V
V
Entry 0
Entry 1
Entry 2
Entry 3
Notes: 1. The D and WT bits are not supported.
2. There is only one PR bit, corresponding to the upper bit of the PR bits in the UTLB.
Figure 7.8 ITLB Configuration
To Next Page
Loading...
Need help?
General
