Renesas SuperH SH-4A - MOVCA.L (Move with Cache Block Allocation): Data Transfer Instruction

Rev. 1.50, 10/04, page 276 of 448
10.1.35 MOVCA.L (Move with Cache Block Allocation): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
MOVCA.L R0,@Rn R0 → (Rn)
(without fetching cache
block)
0000nnnn11000011 1 —
Description: This instruction stores the contents of general register R0 in the memory location
indicated by effective address Rn. This instruction differs from other store instructions as follows.
If write-back is selected for the accessed memory, and a cache miss occurs, the cache block will
be allocated but an R0 data write will be performed to that cache block without performing a block
read. Other cache block contents are undefined.
Notes: None
Operation:
MOVCAL(int n) /*MOVCA.L R0,@Rn */
{
if ((is_write_back_memory(R[n]))
&& (look_up_in_operand_cache(R[n]) == MISS))
allocate_operand_cache_block(R[n]);
Write_Long(R[n], R[0]);
PC += 2;
}
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Data address error