Rev. 1.50, 10/04, page 352 of 448
10.2.7 STS (Store from FPU System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
STS FPUL,Rn FPUL → Rn 0000nnnn01011010 1 —
STS FPSCR,Rn FPSCR → Rn 0000nnnn01101010 1 —
STS.L FPUL,@-Rn Rn-4 → Rn, FPUL → (Rn) 0100nnnn01010010 1 —
STS.L FPSCR,@-Rn Rn-4 → Rn, FPSCR → (Rn) 0100nnnn01100010 1 —
Description: This instruction stores FPU system register FPUL or FPSCR in the destination.
Notes: None
Operation:
STSFPUL(int n, int *FPUL) /* STS FPUL,Rn */
{
R[n] = *FPUL;
PC += 2;
}
STSMFPUL(int n, int *FPUL) /* STS.L FPUL,@-Rn */
{
R[n] -= 4;
Write_Long(R[n],*FPUL) ;
PC += 2;
}
STSFPSCR(int n) /* STS FPSCR,Rn */
{
R[n] = FPSCR & 0x003FFFFF;
PC += 2;
}
STSMFPSCR(int n) /* STS.L FPSCR,@-Rn */
{
R[n] -= 4;
Write_Long(R[n],FPSCR & 0x003FFFFF)
PC += 2;
}
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