Rev. 1.50, 10/04, page 22 of 448
2.7 Usage Notes
2.7.1 Notes on Self-Modified Codes
The SH-4A prefetches instructions to accelerate the processing speed. Therefore if the instruction
in the memory is modified and it is executed immediately, then the pre-modified code in the
prefetch buffer may be executed. And the SH4AL-DSP supports each instruction and operand
cache, the coherency should be considered. In order to reflect the modified code definitely, one of
the following sequences should be executed.
In Case the Modified Codes are in Non-Cacheable Area:
SYNCO
ICBI @Rn
The target for the ICBI instruction can be any address within the range where no address error
exception occurs.
In Case the Modified Codes are in Cacheable Area (Write-Through):
SYNCO
ICBI @Rn
All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI
instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes.
In Case the Modified Codes are in Cacheable Area (Copy-Back):
OCBP @Rm or OCBWB @Rm
SYNCO
ICBI @Rn
All operand cache areas corresponding to the modified codes should be written back to the main
memory by the OCBP or OCBWB instruction. Then all instruction cache areas corresponding to
the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB, and ICBI
instruction should be issued to each cache line. One cache line is 32 bytes.
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