Rev. 1.50, 10/04, page 1 of 448
Section 1 Overview
1.1 Features
The SH-4A is a 32-bit RISC (reduced instruction set computer) microprocessor that is upward
compatible with the SH-1, SH-2, SH-3, and SH-4 microcomputers at instruction set code level. Its
16-bit fixed-length instruction set enables program code size to be reduced by almost 50%
compared with 32-bit instructions. The features of the SH-4A are listed in table 1.1.
Table 1.1 Features
Item Features
CPU
• Renesas Technology original architecture
• 32-bit internal data bus
• General-register files:
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Seven 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set (upward compatible with the SH-1, SH-2, SH-3,
and SH-4 microcomputers)
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instructions
 Instructions executed with conditions
 Instruction set based on the C language
• Super scalar which executes two instructions simultaneously including the
FPU
• Instruction execution time: Two instructions per cycle (max)
• Virtual address space: 4 Gbytes
• Space identifier ASID: 8 bits, 256 virtual address spaces
• On-chip multiplier
• Seven-stage pipeline
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