Rev. 1.50, 10/04, page 219 of 448
10.1.10 BT/S (Branch if True with Delay Slot): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BT/S label If T = 1,
PC + 4 + disp × 2 → PC
If T = 0, nop
10001101dddddddd 1 —
Description: This is a conditional branch instruction that references the T bit. The branch is taken
if T = 1, and not taken if T = 0.
The PC source value is the BT/S instruction address. As the 8-bit displacement is multiplied by
two after sign-extension, the branch destination can be located in the range from –256 to +254
bytes from the BT/S instruction.
Notes: As this is a delayed branch instruction, when the branch condition is satisfied, the
instruction following this instruction is executed before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction.
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.
If the branch destination cannot be reached, the branch must be handled by using BT/S in
combination with a BRA or JMP instruction, for example.
Operation:
BTS(int d) /* BTS disp */
{
int disp;
unsigned temp;
temp = PC;
if ((d&0x80)==0)
disp = (0x000000FF & d);
else disp = (0xFFFFFF00 | d);
if (T==1)
PC = PC + 4 + (disp<<1);
else PC += 4;
Delay_Slot(temp+2);
}
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