Rev. 1.50, 10/04, page 15 of 448
Bit Bit Name
Initial
Value R/W Description
15 FD 0 R/W FPU Disable Bit
When this bit is set to 1 and an FPU instruction is not in
a delay slot, a general FPU disable exception occurs.
When this bit is set to 1 and an FPU instruction is in a
delay slot, a slot FPU disable exception occurs. (FPU
instructions: H'F*** instructions and LDS (.L)/STS(.L)
instructions using FPUL/FPSCR)
14 to 10 — All 0 R Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
9 M 0 R/W M Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
8 Q 0 R/W Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
7 to 4 IMASK All 1 R/W Interrupt Mask Level Bits
An interrupt whose priority is equal to or less than the
value of the IMASK bits is masked. It can be chosen by
CPU operation mode register (CPUOPM) whether the
level of IMASK is changed to accept an interrupt or not
when an interrupt is occurred. For details, see Appendix
A, CPU Operation Mode Register (CPUOPM).
3, 2 — All 0 R Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
1 S 0 R/W S Bit
Used by the MAC instruction.
0 T 0 R/W T Bit
Indicates true/false condition, carry/borrow, or
overflow/underflow.
For details, see section 3, Instruction Set.
Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined): The
contents of SR are saved to SSR in the event of an exception or interrupt.
Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined): The
address of an instruction at which an interrupt or exception occurs is saved to SPC.
Global Base Register (GBR) (32 bits, Initial Value = Undefined): GBR is referenced as the
base address of addressing @(disp,GBR) and @(R0,GBR).
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