Renesas SuperH SH-4A - Figure 4.2 Instruction Execution Patterns (2)

Rev. 1.50, 10/04, page 46 of 448
(2-1) 1-step operation (EX type): 1 issue cycle
I1 I2 ID E1 E2 E3
WB
I1 I2 ID
s1 s2 s3
WB
I1 I2 ID
WB
I1 I2 ID E1/S1 E2/s2 E3/s3
E1/s1 E2/s2 E3/S3
WB
(2-2) 1-step operation (LS type): 1 issue cycle
(2-3) 1-step operation (MT type): 1 issue cycle
(2-4) MOV (MT type): 1 issue cycle
EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#,
NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT
MOV#, NOP
MOVA
MOV
Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative
addressing mode
Figure 4.2 Instruction Execution Patterns (2)