Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 52 of 448
(6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle
I1 I2 ID s1 s2 s3
FS1 FS2 FS3 FS4
FS
(6-13) FLDI0, FLDI1: 1 issue cycle
(6-14) Single-precision floating-point computation: 1 issue cycle
(6-15) Single-precision FDIV/FSQRT: 1 issue cycle
(6-16) Double-precision floating-point computation: 1 issue cycle
(6-17) Double-precision floating-point computation: 1 issue cycle
(6-18) Double-precision FDIV/FSQRT: 1 issue cycle
I1 I2 ID s1 s2 s3
FS1 FS2 FS3 FS4
I1 I2
ID
FE1 FE2 FE3 FE4 FE5
FE6 FS
FEDS (Divider occupied cycle)
FS
FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG
FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS
FMUL
FEDS (Divider occupied cycle)
I1 I2
ID
FE1 FE2 FE3 FE4 FE5
FE6 FS
I1 I2
ID
FE1 FE2 FE3 FE4 FE5 FE6
FS
FE3 FE4 FE5
FE6 FS
FE1
FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
FE1 FE2 FE3 FE4 FE5 FE6 FS
I1 I2
ID
FE1 FE2 FE3 FE4 FE5 FE6
FE3 FE4 FE5 FE6 FS
FE3 FE4 FE5 FE6 FS
I1 I2
ID
FS
Figure 4.2 Instruction Execution Patterns (8)

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English