Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 48 of 448
(4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I1 I2 ID s1 s2 s3
WB
(4-2) LDC to DBR/SGR: 4 issue cycles
I1 I2 ID s1 s2 s3
WB
(4-3) LDC to GBR: 1 issue cycle
(4-4) LDC to SR: 4 issue cycles + 3 branch cycles
ID
ID
ID
I1 I2 ID s1 s2 s3
WB
I1 I2 ID S1 S2 S3
WB
(4-5) LDC.L to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I1 I2 ID E1s1 E2s2 E3s3 WB
ID
ID
ID
(4-6) LDC.L to DBR/SGR: 4 issue cycles
(4-7) LDC.L to GBR: 1 issue cycle
I1 I2 ID S1 S2 S3 WB
ID
ID
ID
I1 I2 ID E1S1 E2S2 E3S3 WB
ID
ID
ID
ID
ID
I1 I2 ID S1 S2 S3
WB
(4-8) LDC.L to SR: 6 issue cycles + 3 branch cycles
(I1) (ID)(I2)
(Branch to the
next instruction.)
(Branch to the next instruction.)
(I1) (ID)(I2)
Figure 4.2 Instruction Execution Patterns (4)

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English