Rev. 1.50, 10/04, page 16 of 448
Vector Base Register (VBR) (32 bits, Privileged Mode, Initial Value = H'00000000): VBR is
referenced as the branch destination base address in the event of an exception or interrupt. For
details, see section 5, Exception Handling.
Saved General Register 15 (SGR) (32 bits, Privileged Mode, Initial Value = Undefined): The
contents of R15 are saved to SGR in the event of an exception or interrupt.
Debug Base Register (DBR) (32 bits, Privileged Mode, Initial Value = Undefined): When the
user break debugging function is enabled (CBCR.UBDE = 1), DBR is referenced as the branch
destination address of the user break handler instead of VBR.
2.2.5 System Registers
Multiply-and-Accumulate Registers (MACH and MACL) (32 bits, Initial Value =
Undefined): MACH and MACL are used for the added value in a MAC instruction, and to store
the operation result of a MAC or MUL instruction.
Procedure Register (PR) (32 bits, Initial Value = Undefined): The return address is stored in
PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine
return instruction (RTS).
Program Counter (PC) (32 bits, Initial Value = H'A0000000): PC indicates the address of the
instruction currently being executed.
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