Rev. 1.50, 10/04, page 342 of 448
10.2 CPU Instructions (FPU related)
Of the SH-4A CPU's instructions, those which support the FPU and those which differ in function
from instructions of the SH3A-DSP are described in this section.
10.2.1 BSR (Branch to Subroutine): Branch Instruction (Delayed Branch Instruction)
Format Operation Instruction Code Cycle T Bit
BSR label PC+4 → PR,
PC+4+disp×2 → PC
1011dddddddddddd 1 —
Description: This instruction branches to address (PC + 4 + displacement × 2), and stores address
(PC + 4) in PR. The PC source value is the BSR instruction address. As the 12-bit displacement is
multiplied by two after sign-extension, the branch destination can be located in the range from –
4096 to +4094 bytes from the BSR instruction. If the branch destination cannot be reached, this
branch can be performed with a JSR instruction.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
BSR(int d) /* BSR disp */
{
int disp;
unsigned int temp;
temp = PC;
if ((d&0x800)==0)
disp = (0x00000FFF & d);
else disp = (0xFFFFF000 | d);
PR = PC + 4;
PC = PC + 4 + (disp<<1);
Delay_Slot(temp + 2);
}
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