Rev. 1.50, 10/04, page 187 of 448
Section 9 L Memory
The SH-4A includes on-chip L-memory which stores instructions or data.
Note: For the size of L-memory, see the hardware manual of the target product.
9.1 Features
• Capacity
Total L memory can be selected from 16 Kbytes, 32 Kbytes, 64 Kbytes, or 128 Kbytes.
• Page
The L memory is divided into two pages (pages 0 and 1).
• Memory map
The L memory is allocated in the addresses shown in table 9.1 in both the virtual address space
and the physical address space.
Table 9.1 L Memory Addresses
Memory Size (Two Pages Total)
Page 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes
Page 0 of L
memory
H'E500E000 to
H'E500FFFF
H'E500C000 to
H'E500FFFF
H'E5008000 to
H'E500FFFF
H'E5000000 to
H'E500FFFF
Page 1 of L
memory
H'E5010000 to
H'E5011FFF
H'E5010000 to
H'E5013FFF
H'E5010000 to
H'E5017FFF
H'E5010000 to
H'E501FFFF
• Ports
Each page has three independent read/write ports and is connected to each bus. The instruction
bus is used when L memory is accessed through instruction fetch. The operand bus is used
when L memory is accessed through operand access. The SuperHyway bus is used for L
memory access from the SuperHyway bus master module.
• Priority
In the event of simultaneous accesses to the same page from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus > operand
bus > instruction bus.
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