Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 325 of 448
10.1.71 STS (Store System Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
STS MACH,Rn MACH → Rn 0000nnnn00001010 1 —
STS MACL,Rn MACL → Rn 0000nnnn00011010 1 —
STS PR,Rn PR → Rn 0000nnnn00101010 1 —
STS.L MACH,@-Rn Rn - 4 → Rn, MACH → (Rn) 0100nnnn00000010 1 —
STS.L MACL,@-Rn Rn - 4 → Rn, MACL → (Rn) 0100nnnn00010010 1 —
STS.L PR,@-Rn Rn - 4 → Rn, PR → (Rn) 0100nnnn00100010 1 —
Description: This instruction stores system register MACH, MACL, or PR in the destination.
Notes: None
Operation:
STSMACH(int n) /* STS MACH,Rn */
{
R[n] = MACH;
PC += 2;
}
STSMACL(int n) /* STS MACL,Rn */
{
R[n] = MACL;
PC += 2;
}
STSPR(int n) /* STS PR,Rn */
{
R[n] = PR;
PC += 2;
}