Rev. 1.50, 10/04, page 297 of 448
10.1.52 PREFI (Prefetch Instruction Cache Block): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
PREFI @Rn Invalidation of instruction
cache indicated by logical
address Rn
0000nnnn11010011 10 —
Description: This instruction reads a 32-byte block of data starting at a 32-byte boundary within
the instruction cache. The lower 5 bits of the address specified by Rn are masked by zeroes.
This instruction does not generate data address error and MMU exceptions. In the event of an
error, the PREFI instruction is treated as an NOP (no operation) instruction.
When the address to be prefetched is missing from UTLB or is protected, the PREFI instruction is
treated as an NOP instruction and a TLB exception does not occur.
Notes: None
Operation:
PREFI(int n) /* PREFI @Rn*/
{
prefetch_instruction_cache_block(R[n]);
PC += 2;
}
Example:
MOVA WakeUp,R0 ; Wakeup address
PREFI @R0 ; Prefetching of instructions to be
executed after release from the SLEEP state
SLEEP
WakeUp:
NOP
This instruction is used, before the SLEEP command is issued, to
prefetch instructions for execution on return from the SLEEP state.
Possible Exceptions:
• Slot illegal instruction exception
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