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Rev. 1.50, 10/04, page 119 of 448

The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data

array. For details, see section 8.6.4, OC Data Array.

The area from H'F600 0000 to H'F60F FFFF is used for direct access to the unified TLB address

array. For details, see section 7.6.3, UTLB Address Array.

The area from H'F610 0000 to H'F61F FFFF is used for direct access to the PMB address array.

For details, see section 7.7.5, Memory-Mapped PMB Configuration.

The area from H'F700 0000 to H'F70F FFFF is used for direct access to unified TLB data array.

For details, see section 7.6.4, UTLB Data Array.

The area from H'F710 0000 to H'F71F FFFF is used for direct access to the PMB data array. For

details, see section 7.7.5, Memory-Mapped PMB Configuration.

The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register

area. For details, see register descriptions in each section of the hardware manual of the target

product.

Physical Address Space: The SH-4A supports a 29-bit physical address space. The physical

address space is divided into eight areas as shown in figure 7.5. Area 7 is a reserved area. For

details, see the Bus State Controller (BSC) section of the hardware manual of the target product.

Only when area 7 in the physical address space is accessed using the TLB, addresses H'1C00 0000

to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the control

H'0000 0000

H'0400 0000

H'0800 0000

H'0C00 0000

H'1000 0000

H'1400 0000

H'1800 0000

H'1C00 0000

H'1FFF FFFF

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7 (reserved area)

Figure 7.5 Physical Address Space

Renesas SuperH SH-4A User Manual

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