Renesas SuperH SH-4A - Register Descriptions; Table 9.2 Register Configuration; Table 9.3 Register Status in each Processing State

Rev. 1.50, 10/04, page 188 of 448
9.2 Register Descriptions
The following registers are related to L memory.
Table 9.2 Register Configuration
Name Abbreviation R/W P4 Address*
Area 7
Address* Access Size
On-chip memory control
register
RAMCR R/W H'FF000074 H'1F000074 32
L memory transfer source
address register 0
LSA0 R/W H'FF000050 H'1F000050 32
L memory transfer source
address register 1
LSA1 R/W H'FF000054 H'1F000054 32
L memory transfer
destination address register
0
LDA0 R/W H'FF000058 H'1F000058 32
L memory transfer
destination address register
1
LDA1 R/W H'FF00005C H'1F00005C 32
Note: * The P4 address is the address used when using P4 area in the virtual address space.
The area 7 address is the address used when accessing from area 7 in the physical
address space using the TLB.
Table 9.3 Register Status in Each Processing State
Name Abbreviation
Power-On
Reset Manual Reset Sleep Standby
On-chip memory control
register
RAMCR H'00000000 H'00000000 Retained Retained
L memory transfer source
address register 0
LSA0 Undefined Undefined Retained Retained
L memory transfer source
address register 1
LSA1 Undefined Undefined Retained Retained
L memory transfer
destination address register
0
LDA0 Undefined Undefined Retained Retained
L memory transfer
destination address register
1
LDA1 Undefined Undefined Retained Retained